1. Field of the Invention
Embodiments of the present invention generally relate to electrostatic discharge (ESD) protection, and more particularly to ESD protection of power amplifier integrated circuits.
2. Description of the Related Art
Electrostatic discharge (ESD) occurs when a static charge builds up in a human operator or machine and then through contact produces a large current in an integrated circuit in a short period of time. ESD may damage an unprotected complementary metal oxide semiconductor (CMOS) integrated circuit, and shrinking CMOS process technologies result in structures more susceptible to ESD damage. At the same time, increasing signaling rates of high speed communications systems require strict control of signal distortion to ensure adequate performance. A well designed ESD protection circuit should not alter significantly a transmit signal or a receive signal passing through the node the circuit protects.
A typical ESD clamp circuit shunts the large current generated by the ESD event to ground bypassing the sensitive blocks of the integrated circuit thereby protecting them from the ESD event. Coupling such an ESD clamp circuit directly to an input or output node may provide a large capacitive load to a high frequency input or output signal coupled to the same node, thereby distorting the signal. Intervening circuitry between the ESD clamp circuit and the input or output node may isolate the ESD clamp circuit's capacitance from the high frequency signal.
FIG. 1 illustrates a prior art ESD protected integrated circuit 100 that couples an ESD clamp circuit 102 to a radio frequency output (RF OUT) package pin 104 through a first inductive bond wire Lbw 106 between a chip pad 108 and the RF OUT package pin 104. Similarly a high frequency transmit signal output from a power amplifier (PA) 101 is coupled to the RF OUT package pin 104 through a second inductive bond wire Lbw 105 coupled between a chip pad 103 and the RF OUT package pin 104. During radio frequency (RF) operation, the bond wire inductors Lbw 105 and Lbw 106 ensure that the PA 101 output couples to an off-chip impedance matching network (not shown), which couples to the RF OUT package pin 104, thereby shielding the ESD clamp circuit 102 from the high peak voltages of the PA 101 transmit signal. During an ESD event, the low frequency current generated at the RF OUT package pin 104 is absorbed by the ESD clamp circuit 102, thereby protecting the PA 101 from damage by the ESD.
Many different designs exist in the prior art for ESD clamp circuits, which may activate when a voltage at the input to the ESD clamp circuit 102 exceeds a certain level, turning on a clamp transistor circuit within the ESD clamp circuit 102 and thereby shunting excess current due to a voltage differential to ground. The ESD clamp circuit 102 may present a significant capacitive load if connected directly to the PA 101, thereby affecting the performance of the PA 101. The bypass capacitor 107 coupled to the same chip pad as the ESD clamp 102 minimizes the load of the ESD clamp circuit 102 on the PA 101. Packages without bond wires, such as chip scale packages, however, do not use bond wires to couple the chip pads to the package inputs/output nodes. Instead the chip pads couple directly to the package bumps, and as such an alternative ESD protection circuit is required.
FIG. 2 illustrates another prior art ESD protected integrated circuit 200, for a chip packaged without bond wires, in which an ESD clamp circuit 202 couples through an on-chip inductor Loc 204 to an RF OUT chip pad 203 to which a PA 201 output is coupled as well. The ESD clamp circuit 202 may not couple directly to the RF OUT chip pad 203, as its capacitance may load undesirably the PA 201 output signal thereby affecting the PA 201 output signal's transmission characteristics. The on-chip inductor Loc 204 may isolate the PA 201 from the ESD clamp circuit's 202 capacitance, but disadvantageously, the on-chip inductor Loc 204 may require significant chip area to implement. Additionally, the resistance of the on-chip inductor Loc 204 may result in an undesirable voltage drop across the inductor Loc 204 during the ESD event, which may compromise the level of ESD protection. Therefore there is a need for an ESD protection circuit for CMOS IC power amplifiers that ensure high performance signal transmission and adequate ESD protection while requiring minimal chip area.